1. Field of the Invention
The invention relates generally to sigma-delta digital-to-analog converter systems. More particularly, it relates to a method and apparatus for implementing non-integer sample/hold operations in sigma-delta digital-to-analog converter systems, which is computationally efficient and produces effective performance with simple filters.
2. Description of the Prior Art
Over the past decade or more, the use of digital technology in the audio industry has become very widespread. This has led to the development of a number of industrial standards at which audio inputs are sampled, such as at the rates of 11.025, 22.05, or 44.1 KHz for consumer audio equipment or at the rates of 8, 16, 32 or 48 KHz for professional digital equipment. It is frequently desired to mix audio samples having different sample rates. Consequently, there has arisen the need of sample-rate conversion (SRC) systems for converting one of the audio samples to the sample rate of another audio sample for allowing mixing to be performed.
Some sample rates can be easily converted, such as when a second sample rate is an integer multiple of a first sample rate. For example, in a normal system where the modulator of a sigma-delta digital-to-analog converter (DAC) system is operated at one-half of a master clock having a frequency of 12.288 MHz, the input sample rate of 96 KHz is easily converted or upsampled by 64 in order to obtain the 6.144 MHz sample rate at the modulator. However, in the case of a system where a universal serial bus (USB) is used, the master clock has a frequency of 12 MHZ. Therefore, the input sample rate of 96 KHz cannot be easily converted or upsampled to 6 MHz since this requires multiplying by a non-integer ratio of 125/8 or 15.525. For general information and discussion of multi-rate digital signal processors as regards to systems for decimation and interpolation, reference is made to an article by Ronald E. Crochiere and Lawrence R. Rabiner, “Interpolation and Decimation of Digital Signals—A Total Review”, Proceeding of the IEEE, Vol. 69, No. 3, March 1981, p. 300-331.
For discussion purposes, as is illustrated in FIG. 1, the front-end portion of a conventional sigma-delta digital-to-analog converter system 10 includes an interpolation filter 12 that increases the sampling rate of a digital input signal (i.e., a low-rate 24-bit input signal) by a predetermined upsampling ratio (i.e., 4) to a high sampling rate and that has a good anti-aliasing performance so as to reject images that occur at approximately the Nyquist rate of the input signal. The higher rate digital signal is then transmitted to a sample/hold block 14 having an output that is fed to a high-rate sigma-delta modulator 16 which shapes quantization noise out of the input signal band and reduces the sample to a 4-bit output signal.
In this particular configuration, the interpolation filter 12 effectively pushes aliases of the input signal to around 4−fs and beyond so that a substantial amount of the noise power is translated to frequency bands well above the signal band of interest. The sample/hold block 14 is used to upsample the output of the interpolation filter to the rate at which the modulator operates and provide additional attenuation to the aliases. The amounts of attenuation required on the aliases at around and above 4−fs are relatively low due to the high pass filtering of the quantization noise in the sigma-delta modulator 16.
As can be seen, with an input sample rate of 96 KHz for a 12 MHz master clock frequency and after the upsample of 4 by the interpolation filter, there is required a non-integer sample/hold ratio of 125/8 or 15.625 in order to obtain a 6 MHZ sampling rate at the modulator. Heretofore, there have been provided a number of traditional digital filter architectures used for interpolation and decimation in which the ratios are integers. However, there are presented problems with computational complexity and efficient implementation with the traditional architectures when the ratios are non-integers.
It would therefore be desirable to provide a new and novel filtering approach which can be used to implement non-integer sample/hold operations without requiring a high number of computations to be performed and thus can be realized by relatively simple filters. It would also be expedient to provide a polyphase filter in which only a few output samples immediately after an input transition is required to be calculated so as to provide computational efficiency.